1. Field of the Invention
The invention relates to memories, and more particularly to buffer management for memories.
2. Description of the Related Art
Memories are common components of electronic systems. An electronic system with a memory may comprise multiple component devices requiring accessing of the memory. The memory, however, can only service an access request of one of the component devices at a time. Therefore, when multiple component devices of the electronic system require accessing of the memory at the same time, a buffer management apparatus is provided to handle the memory access requests of the multiple component devices.
Referring to FIG. 1, a block diagram of an electronic system 100 with a conventional buffer management apparatus 104 is shown. In additional to the buffer management apparatus 104, the electronic system 100 comprises a plurality of circuit blocks 102a˜102n, a memory controller 106, and a memory 108. Each of the circuit blocks 102a˜102n connects to a component device of the electronic system 100 and generates an access request signal sent to the arbiter 104 when the component device wants to access the memory 108. The access request signal (Req) comprises request mode information (Mode) indicating what type an access request is received, such as a read request, a write request, a byte read quest, a byte write quest, a mask read quest, or a mask write quest, and data (Odata) which is to be written to the memory 108.
The buffer management apparatus 104 comprises an arbiter 112, a mode latch circuit 114, and an address generator 116. When the arbiter 112 receives multiple access request signals from the circuit blocks 102a˜102n at the same time, the arbiter 112 selects an owner from the multiple circuit blocks 102a˜102n to send the access requests to the memory 108. After the owner is selected, the arbiter 112 sends a grant signal (Gnt) to the owner to notify the circuit block that its access request is granted. The mode latch circuit 114 then stores the request mode information (Mode) of the access request sent by the owner. The address generator 116 then generates address information (Addr) according to the owner selected by the arbiter 112 and the mode information stored in the mode latch circuit 114, wherein the address information indicates the memory address accessed by the owner.
After the owner is selected, the arbiter 112 generates owner information about the owner which sends the access request. In addition, the arbiter 112 also generates request type information (Req-type) according to the request mode information (Mode) generated by the owner, wherein the request type information also indicates what type of the access request is, such as a read request or a write request. Thus, a memory access request signal comprising the owner information (Owner), the request type information (Req-type), written data (Odata), and the address information (Addr) is formed and delivered to the memory controller 106.
The memory controller 106 then accesses the memory 108 according to the memory access signal and generates a memory response signal in response to the memory access signal. In one embodiment, the memory response signal comprises an address latch enable signal (Ale), a data latch enable signal (Dle) from memory controller 106, and data (Idata) read from the memory 108 according to the memory access signal. The address latch signal informs the owner that a current address has been accessed and requests for a new address. The data latch signal informs the owner that a current data has been output to the owner.
The arbiter 112 then forwards the address latch enable signal (Ale), the data latch enable signal (Dle), and the read-out data (Idata) as an access response signal to the owner selected from the multiple circuit blocks 102a˜102n. The circuit block sends an address increment signal (Ptr-inc) to the address generator 116 to increment the address of the address information (Addr). When all addresses requested by an access request signal have been accessed, the arbiter 112 sends an address latch completion signal (Ale-last) to inform the owner. When all data requested by an access request signal have be read out from the memory 108, the arbiter 112 sends a data latch completion signal (Dle-last) to inform the owner. After all access requests of the current owner is completed, the arbiter 112 selects a next owner capable of accessing the memory 108 from the other circuit blocks 102a˜102n, and the same memory access procedure is repeated for the next owner.
The buffer management apparatus 104 generates address information (Addr) with the mode latch circuit 114 and the address generator 116. If the circuit blocks accessing the memory can generate address information by themselves, the mode latch circuit 114 and the address generator 116 can be omitted from the buffer management apparatus 104. Referring to FIG. 2, a block diagram of an electronic system 200 with another conventional buffer management apparatus 204 is shown. A plurality of circuit blocks 202a˜202n directly generates access requests comprising request type information (Req-type), written data (Odata), and accessed address (Addr). After the arbiter 212 selects an owner of the memory 208 from the circuit blocks 202a˜202n, the arbiter directly forwards the request type information (Req-type), the written data (Odata), and the accessed address (Addr) generated by the owner as a memory access signal sent to the memory controller 206. The mode latch circuit 114 and the address generator 116 therefore do not exist in the buffer management apparatus 204 of FIG. 2.
With the advancement of electronic systems, bandwidth requirements of memories are being increased. However, in order to get higher bandwidth, some performances may be sacrificed to accommodate the timing critical path, such as chip area or power consumption. Thus, a buffer management apparatus interfacing between the memory and the component circuits is required to solve the problem.